FIG. 1 shows a block diagram of a prior art pulse detector 100 such as the National Semiconductor DP8464B device, suitable for use in detecting data from a magnetic disk storage device. The purpose of the pulse detector is to accurately convert peaks in the analog signal from the disk to digital edges of identical time position. This task is accomplished by first determining that a given disk signal is valid (i.e. not noise) and then determining the exact time position of the signal peak. The determination of the signal validity is accomplished in what is often called "gating" or "qualification" channel 199. The extraction of the timing of the peaks is accomplished in what is often called "timing channel" 198. In the case of the DP8464B, qualification channel 199 consists of comparator with hysteresis 102, while timing channel 198 consists of differentiator 111. The timing and gating channels are combined by flip-flop 101 to produce an output data stream.
Pulse detector 100 of FIG. 1 includes differential input leads 105 which serve to receive a differential input signal from a disk or, more typically, a read/write preamplifier which amplifies data signals from a disk during reading. This differential input signal is applied to the differential input leads of gain controlled amplifier 104, whose gain is set by automatic gain control circuit 110. The differential output signal from gain controlled amplifier 104 is applied to differential filter 106, whose differential output signal is applied to gate channel input 107 and time channel input 108.
Differential filter 106 serves to remove noise that lies outside the bandwidth of the read channel signal, thereby preventing noise in the desired signal from being applied to gate channel input 107 and time channel input 108.
A by-product of filter 106 is the amount of group delay it introduces between the output of amplifier 104 and the gate and time channel inputs 107 and 108, which will hereafter be generally referred to as the "channel input."
FIG. 2 shows various waveforms depicting the operation of pulse detector 100 of FIG. 1 operating on a typical hard disk read channel signal. FIG. 2 illustrates how noise in shoulder region 201 (the flat region near base line 202 occurring between peaks 203) is removed from encoded data output signal 207. The process of removing noise is called signal qualification. Signal qualification is accomplished with circuitry devoted to this task. Signal qualification refers to a particular point in time when a decision is made as to whether or not a disk signal is to be considered valid. A valid signal will at some point produce an output signal from pulse detector 100 (FIG. 1). Signal qualification is accomplished by pulse detector 100 by allowing the signal applied to the D input lead of flip-flop 101 to change when the signal applied to differential input lead 105 crosses a predefined hysteresis level (shown as dashed lines 303 in FIGS. 2 and 3). In this way noise 208 occurring in time pulse output signal 204, which serves as the clock signal applied to flip-flop 101 (FIG. 1), only clocks in old data to flip-flop 101. In other words, only time pulse output signal 209 corresponding to peak 203 of the disk waveform is allowed to propagate to encoded data output terminal 103, since noise 208 clocks in the same data as does dara pulse 209 corresponding to peak 203.
For the most part, this type of circuit does a good job of removing baseline noise which occurs in shoulder region 201 of the disk read signal waveform. However, base line noise is not the only type of noise present in a read signal from a disk. FIG. 3 shows a disk signal that contains "off track noise": noise that results from the read head picking up some of the signals on adjacent tracks. The interfering tracks cause false peaks 302 that can occur above hysteresis threshold level 303. False peaks 302 can result in errors because they are not masked by prior art detection circuitry. Thus, with prior art circuits, an encoded data output signal is produced corresponding to false peaks 302 and not the real peak 301.
Another potential problem with prior art detection circuitry is the critical timing relationship between the clock signal (i.e. the timing channel) and the D input signal to flip-flop 101 (i.e. the gating channel). If there is a timing skew such that time pulse output signal 204 (FIG. 2) is delayed in relation to the output signal from comparator with hysteresis 205, then it is possible, for noise in shoulder region 201 to generate errors on encoded data output signal 207 available on output lead 103. FIG. 4 illustrates how this can happen. FIG. 4 shows a noise spike PA occurring below hysteresis threshold 303 and prior to the true disk signal peak PB. Differentiator 111 responds to all signal peaks including noise spike PA and produces an output signal that is applied to the clock input lead of flip-flop 101. The output signal from differentiator 111, however, is delayed by any delay in the logic in the path between the output of differentiator 111 and the clock input lead of flip-flop 101 and RC network 114, 115 (typically formed as external components). This delay is indicated as Td in FIG. 4.
The signal applied to the D input lead of flip-flop 101 serves as the qualification signal. For the circuit of FIG. 1, qualification occurs when the disk read signal crosses the appropriate hysteresis threshold level. Because of delay Td, the clock signal due to PA occurs after the signal applied to the D input lead of flip-flop 101 changes state. Consequently, the clock signal due to noise spike PA clocks in the new data to flip-flop 101. The true peak at PB clocks in old data and the state of flip-flop 101 does not change. Consequently, pulse detector 100 provides an incorrect pulse PI at the data output lead, corresponding to noise spike PA and not true peak PB, even though noise spike PA was below the qualification level set by hysteresis threshcld level 303. In this event, the correct pulse PC corresponding to peak PB is not provided.